1. Field of the Invention
The present invention relates to a cascode amplifying circuit and a folded cascode amplifying circuit.
2. Description of the Related Art
Currently, a cascode amplifying circuit constituted by MOS transistors is widely utilized with an increase in operational frequency of various integrated circuit apparatus since delay of signal by influence of a gate capacitance is comparatively inconsiderable.
According to a basic constitution of a cascode amplifying circuit, as shown by FIG. 5, MOS transistors m1 and m2 of the same conductive type, for example, N-channel type are connected in cascode, an input signal is applied to the gate of the MOS transistor m1 on a side of connecting the source to a power source terminal VSS (0V), and an output terminal is provided to the drain of the MOS transistor m2 the drain of which is connected with a current source and the gate of which is applied with bias voltage. Amplifying gain of such a cascode amplifying circuit is increased by applying negative feedback from the source to the gate of the output transistor of the cascode amplifying circuit. A description will be given thereof as follows.
In FIG. 5, the gate terminal of the MOS transistor m2 is applied with fixed bias voltage Vbias. Now, when transfer conductances of the MOS transistors m1 and m2 are respectively designated by notations gm1 and gm2, output resistance values thereof are respectively designated by notations r01 and r02, further, an output resistance value of the cascode amplifying circuit is designated by notation r0, the amplifying gain of the cascode amplifying circuit is represented by gm1xc2x7r0. Here, when r0 is represented by r01 and r02, the following equation is established.
r0=r01+(1+gm2xc2x7r01)xc2x7r02≈gm2xc2x7r01xc2x7r02xe2x80x83xe2x80x83(1)
Therefore, the amplifying gain of the cascode amplifying circuit is represented by the following equation.
gm1xc2x7r0≈gm1xc2x7gm2xc2x7r01xc2x7r02xe2x80x83xe2x80x83(2)
Now, when negative feedback having gain A is applied from the source to the gate of the MOS transistor m2 instead of applying the fixed bias voltage Vbias to the gate terminal of the MOS transistor m2, the output resistance value r0 is changed as follows.
xe2x80x83r0=r01+(1+(1+A)xc2x7gm2xc2x7r01)xc2x7r02≈Axc2x7gm2xc2x7r01xc2x7r02xe2x80x83xe2x80x83(3)
Therefore, the amplifying gain of the cascode amplifying circuit becomes as follows.
gm1xc2x7r0≈Axc2x7gm1xc2x7gm2xc2x7r01xc2x7r02xe2x80x83xe2x80x83(4)
It is known that the amplifying gain is increased by a multiplication factor of about A by applying the negative feedback. This can be changed to state as follows. That is, although the change in the output resistance value of the MOS transistor m2 in accordance with the change in the output value of the cascode amplifying circuit, brings about the change in source voltage of the MOS transistor m2, the negative feedback from the source to the gate of the MOS transistor m2 operates to restrain a change depending on an output value of the output resistance value of the MOS transistor m2. As a result, the output resistance of the cascode amplifying circuit looks as high resistance and the amplifying gain is increased.
Meanwhile, an operational range of the output of the circuit of FIG. 5 is determined by a condition by which the MOS transistor m1 is brought into a saturated region. That is, when voltage of a drain node x of the MOS transistor m1 is designated by notation Vx, gate/source voltage of the MOS transistor m1 is designated by Vgs1 and threshold voltage thereof is designated by notation Vth1, the operational range is prescribed by Vx greater than Vgs1xe2x88x92Vth1.
In an actual cascode amplifying circuit, the above-described negative feedback is realized as shown by FIG. 6 and FIG. 7.
FIG. 6 shows a cascode amplifying circuit increasing amplifying gain by the simplest constitution. According to the constitution, a cascode amplifying circuit comprising the MOS transistors m1 and m2 and an active load i1, is applied with negative feedback by an amplifying circuit comprising an MOS transistor m3 and an active load i2. Now, when the resistance value of the MOS transistor m2 is reduced by, for example, a change in output voltage, although voltage of the node x starts increasing, the gate voltage of the MOS transistor m2 is reduced by operation of the negative feedback and accordingly, the resistance value of the MOS transistor m2 is restrained from reducing. In this way, the negative feedback by the amplifying circuit comprising the MOS transistor m3 and the active load i2, operates to restrain the change in the resistance value of the MOS transistor m2 and achieves an effect of increasing the amplifying gain. However, in the circuit of FIG. 6, the voltage Vx of the drain x of the MOS transistor m1 must satisfy at least a voltage relationship of Vx greater than Vth3 (notation Vth3 designates threshold voltage of the MOS transistor m3) in order to guarantee operation of the MOS transistor m3 and there poses a problem that an output operational range becomes narrower than that in the case of the circuit of FIG. 5. Further, there poses a problem that frequency of pole at the node x is lowered and response of the cascode amplifying circuit is delayed by a mirror effect with respect to gate/drain capacitance of the MOS transistor m3. Furthermore, although according to the constitution of FIG. 6, the source terminal voltage Vx of the MOS transistor m2 is determined by the MOS transistor m3 and the active load i2, there also poses a problem that the value of Vx is dispersed by device dispersion of the MOS transistor m3 or a change in a value of the active load i2.
FIG. 7 shows a cascode amplifying circuit improved to increase amplifying gain while avoiding the problems of the circuit of FIG. 6. According to the constitution, in the cascode amplifying circuit comprising the MOS transistors m1 and m2 and the active load i1, negative feedback is applied to the transistor m2 by a folded cascode amplifying circuit constituted by using the MOS transistor m3 having a conductive type reverse to that of the MOS transistors m1 and m2. Since the MOS transistor m3 is the MOS transistor having the conductive type reverse to that of the MOS transistor m1, there is achieved an advantage that lowering of the drain voltage of the MOS transistor m1 does not hamper operation of the MOS transistor m3 and the output voltage range of the cascode amplifying circuit is not narrowed by the negative feedback circuit. Further, since the drain node of the MOS transistor m3 is connected to the source of an MOS transistor m12 in cascode, there is achieved an advantage that the mirror effect with respect to the gate/drain capacitance of the MOS transistor m3 is restrained. Further, the negative feedback portion of FIG. 7 is provided with a differential input portion constituted by the MOS transistor m3 and an MOS transistor m11 and accordingly, there is achieved an advantage that by applying fixed bias voltage to the gate terminal of the MOS transistor m11, the source terminal voltage of the MOS transistor m2 can be adjusted.
However, a large number of transistor elements are needed in the constitution of FIG. 7 and not only the circuit scale is excessively large but also the constitution is constructed by a multiple stage series connection of the transistors and accordingly, there poses a problem that operation at low power source voltage becomes difficult.
According to an aspect of the invention, there is provided a cascode amplifying circuit comprising a first, a second and a third MOS transistor having a same conductive type, and a fourth MOS transistor having a conductive type reverse thereto, wherein a source of the second MOS transistor is connected to a drain of the first MOS transistor and a drain of the second MOS transistor is connected to an output terminal, there is provided a differential amplifying circuit a first differential input terminal of which is constituted by a gate of the third MOS transistor, a second differential input terminal of which is constituted by a source thereof and a differential output terminal of which is constituted by a drain thereof, there is provided a load circuit constituted by connecting a source of the fourth MOS transistor to the differential output terminal, there is provided an inverted amplifying circuit for invertedly amplifying an output from the differential output terminal via the load circuit, and there is provided a negative feedback circuit from the source of the second MOS transistor to a gate thereof by applying a predetermined fixed bias voltage to the first differential input terminal, connecting the second differential input terminal to the source of the second MOS transistor and connecting the output terminal of the inverted amplifying circuit to the gate of the second MOS transistor.
According to another aspect of the invention, in the cascode amplifying circuit, it is preferable that an input terminal is constituted by a gate of the first MOS transistor and it is also preferable that an input terminal is provided to a connection point connecting the second differential input terminal of the differential amplifying circuit and the source of the second MOS transistor and a signal current is applied to the input terminal.
Further, according to another aspect of the invention, there is provided a folded cascode amplifying circuit comprising a first through a fourth circuit each comprising the cascode amplifying circuit, wherein each of the first through the third MOS transistors in the first and the second circuits is of a first conductive type and the fourth MOS transistor is of a second conductive type reverse to the first conductive type, each of the first and the third MOS transistors in the third and the fourth circuits is of the second conductive type and the fourth MOS transistor is of the first conductive type, a first common output terminal is constituted by connecting the respective drains of the second respective MOS transistors in the first and the third circuits, a second common output terminal is constituted by connecting the respective drains of the second respective MOS transistors in the second and the fourth circuits, the respective sources of the second respective MOS transistors in the first and the second circuits or the respective sources of the second respective MOS transistors in the third and the fourth circuits are respectively connected to a first and a second input terminal, there is provided a differential circuit constituted by commonly connecting respective sources of a fifth and a sixth respective MOS transistors, respective drains of the fifth and the sixth respective MOS transistors are respectively connected to the first and the second input terminals, the fifth and the sixth respective MOS transistors are of a conductive type reverse to the conductive type of the second respective MOS transistors provided with the first and the second input terminals, a first and a second common input terminal are respectively constituted by respective gates of the fifth and the sixth respective MOS transistors, and an input signal is applied to the first and the second respective common input terminals and an output signal is generated from the first and the second respective common output terminals.